This invention relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device.
As a conventional semiconductor memory device which has a plurality of electrically erasable and programmable read only memory cells, each being capable of storing two bits of information, there is known a cell transistor as shown schematically in FIG. 23. In a channel forming region in a substrate 11, between diffusion regions 12A and 12B in the substrate 11, there are provided an insulating film 13 and a control gate electrode 15, on both sides of which there are provided insulating films 14 and word line electrodes 16.
As for the memory cell of this sort, reference is made for example to
(1) A Novel 2-Bit/Cell MONOS Memory Device with a Wrapped-Control-Gate Structure That Applies Source-Side Hot Electron Injection, 2002 Symposium on VLSI Technology Digest of a Technical Papers, p206 to 207;
(2) Japanese Patent Kokai Publication JP-P2001-230332A (JP Patent Application 2000-269892);
(3) Japanese Patent Kokai Publication JP-P2002-26149A (JP Patent Application 2000-180763);
(4) Japanese Patent Kokai Publication JP-P2001-357681A (JP Patent Application 2000-180760);
(5) U.S. Pat. No. 6,399,441; and
(6) U.S. Pat. No. 6,388,293.
As another configuration of the memory cell, storing two bits of information per cell, such a structure shown in FIG. 24 has been proposed. In the undermentioned publication (10) (Japanese Patent Kohyo Publication JP-P2001-512290A), for example, it is stated that a non-volatile memory of the MONOS (metal-ONO-silicon) structure, including, as a gate insulating film 14, which comprises a silicon oxide film formed on a substrate, a silicone nitride film formed on the silicon oxide film and a silicon oxide film formed on the silicone nitride film, referred to as an oxide nitride oxide (ONO) film, is able to store 2-bit data per cell in a charge trapping film (silicon nitride film) sandwiched between silicon oxide films directly below the gate electrode. In an EEPROM (Electrically Erasable and Programmable Read Only Memory), having a charge trapping film and 2-bit storage node per cell, two separate bits, that is a left side node Node1, and a right side node Node2, are formed in spatially spaced apart regions in the charge trapping film. The two bits (storage nodes) are read in the opposite direction to the direction in which the bits were programmed. For example, the Node2 is programmed in the charge trapping film in the ONO film 14 by applying a positive write voltage across the gate electrode 16 and the drain diffusion region 12B, as the source diffusion region 12A is grounded, for injecting sufficiently accelerated hot electrons into a region adjacent to the drain diffusion region 12B of the charge trapping film in the ONO film 14. The stored bits are read in the opposite direction to the direction in which the bits were written, that is by applying the positive electrode to the source electrode 16 and the source diffusion region 12B, as the drain diffusion region 12B is grounded. The memory cell is erased by applying a suitable erase voltage to for example the gate electrode 16. For erasing the Node2, the erase voltage is applied to the drain diffusion region 12B and, for erasing the Node1, the erase voltage is applied to the drain diffusion region 12A for expelling the electrons from the charge trapping film. Thus, by applying preset gate, drain and the source voltages, two bits can be independently stored in the left and right regions of the charge trapping film directly below the gate electrode.
This sort of the memory cell has been disclosed in for example the
(7) U.S. Pat. No. 6,011,725;
(8) U.S. Pat. No. 6,256,231;
(9) Japanese Patent Kokai Publication JP-P2001-156189A (JP Patent Application 2000-306999); and
(10) Japanese Patent Kohyo Publication JP-P2001-512290A (JP Patent Application 2000-505640).
The 2-bit cell MONOS memory device, described in the above Publication (1), is now explained in detail.
In the above Publication (1), there are shown a cross-sectional view and an equivalent circuit of the MONOS memory of the one-cell two-bit configuration, shown in FIGS. 25A to 25C, as well as the bias conditions for the write, erase and read operations.
The memory cell includes paired impurity diffusion regions (paired bit lines), provided in the substrate surface, plural control gates CG provided on the silicon oxide film between the neighboring diffusion regions in the substrate surface, and plural word lines WL extending in a direction perpendicular to the control gates on the ONO film on both sides of the silicon oxide film in the substrate surface, to carry out programming and erasure for the nodes by source side hot electron injection and by hot hole electron injection, respectively.
In the Publication (1), the respective storage sites below the word line WL[j] on the right hand side of the control gate CG [1+2n] are programmed in parallel. The bit line BL [I+2nxe2x88x921] is set to the ground potential, the bit line BL [I+2n] is biased to 5.0V, while the word line WL[j] is biased to 9.0V. The control gate CG[I+2n] is biased to 1.0V/0.0V to induce/suppress the source side hot electron injection. The information stored on the right hand side of the control gate is erased by hot hole injection produced by the bias conditions of FIG. 25C. During read, the bit line BL[I+2nxe2x88x921] is biased to 1.5V, while the bit line BL [i+2n] is biased to 0.0V, the word line WL[j] is biased to Vread and the control gate CG [I+2n] is biased to 1.5V. For programming/erasing the storage site for the left hand side of the control gate CG [I+2n], the bias conditions for the bit line BL [I+2nxe2x88x921], BL [I+2n] are exchanged. The respective bits of the memory cells are read by applying the reverse read, as indicated in FIG. 25C.
Referring to FIG. 26, the operation of programming in the memory cell, as disclosed in the above Publication (1), is scrutinized. The following shows the results of analyses which are based on the results of the investigations by the present inventor.
FIG. 26A is a diagram showing the structure of a memory cell disclosed in the Publication (1). FIG. 26A is drawn by the present inventor for explaining the operation of memory cell disclosed in the Publication (1). In FIG. 26A, 201 denotes a semiconductor substrate, 202 denotes a N+ diffusion region, also simply referred to as a diffusion region, 203 denotes a gate insulating film, 204 denotes an ONO film, 205 denotes a control gate (electrode) and 206 denotes a word line (electrode). In writing (programming) in the node 1 (Node1), the, voltages of 5V and 0V are applied to the bit lines BL1 and BL2, respectively. The voltage of 9V is applied to the word line 206 (VWL=9V). At this time, the voltage of 1V is applied to the control gate 205 (VCG=1.0V) to suppress the current flowing into the channel to a lower magnitude. FIG. 26B shows an electric field in a channel region in FIG. 26A. FIG. 26B shows a result based on the investigation by the present inventor.
In view of the increased channel resistance, an electric field is concentrated, as shown in FIG. 26B, to inject the electrons into the ONO film 204. The maximum strength point of the electric field occurs on a boundary between the word line 206 and the control gate 205. It is at this location of the electric field concentration that the electrons migrated from the source diffusion region (BL2) are accelerated in the vicinity of the maximum strength of the electric field to exhibit a high energy. The accelerated electrons are sucked by the positive electric field of the word line 206 so as to be trapped in a portion of the ONO film 204 slightly offset towards the drain diffusion region (BL1) from the boundary between the word line 206 and the control gate 205. Meanwhile, writing in the opposite side storage node may be achieved by interchanging the bias voltages applied to the source and the drain.
The site of electron trap in the ONO film 204 (indicated by a black circle specified by the Node1 in FIG. 26A) is near the boundary between the electrode of the word line 206 and the electrode of the control gate 205 and is at a preset distance from the drain diffusion region 202 (BL1).
As described above, the: source side injection phenomenon is exploited in the programming operation.
Referring to FIG. 27, the read operation of the memory cell, disclosed in the Publication (1), is scrutinized. FIG. 27 is a diagram drawn by the present inventor for describing the problem which the present inventor has found in the read operation of the memory cell disclosed in the Publication (1).
In the following explanation, it is assumed that no electrons are trapped in the first node (Node1), and that electrons are trapped in the second node (Node2).
When reading the first node (Node1), the voltages of 1.5V and 0V are applied to the bit lines BL2 and BL1, respectively. That is, read is carried out with the diffusion region 202 of the node to be read as the source. Since no electrons are trapped in the first node (Node1), the read current should flow through the memory cell. However, the electrons trapped by the second node (Node2) affect the potential on the channel surface to render the channel current flow difficult.
In order to avoid this problem, a higher voltage must be applied to the bit line BL2 to extend a depletion layer 207 to render the effect of the electrons trapped in the second node (Node2) less apparent.
On the other hand, the distance between the electron trapping region, located near the boundary between the word line electrode 206 and the control gate electrode 205, and the bit line diffusion region, referred to below as xe2x80x9ctrap spacexe2x80x9d (see FIG. 27), is susceptible to process variations.
If, for example, the trap space is large, a high voltage needs to be applied to the BL diffusion region 202. If, for example, the trap space is on the order of 0.1 xcexcm, the voltage applied needs to be 2 to 3V.
If, due to process variations, the distance of the trap space is varied, the channel current is varied to render it difficult to realize stable circuit operation.
The relationship between the trap space and the channel current is now explained based on the results of analyses by the present inventor.
FIG. 28A shows voltage to current (V-I) characteristics of the memory cell transistor when no electrons have been trapped in the first node (Node1) nor in the second node (Node2). The characteristics shown are those of the usual transistor. Meanwhile, the voltage to current (V-I) characteristics of FIG. 28 show measured values of a device tentatively produced by the present inventor.
On the other hand, FIG. 28B shows characteristics of the channel current (indicated on the ordinate) when electrons are trapped in only the second node (Node2) and when the drain voltage (indicated on the abscissa) is applied to the second node (Node2). The same voltage Vg is applied to the control gate and to the word lines.
The trap space of this memory cell is estimated to be approximately 0.03 to 0.05 xcexcm. Thus, if the trap space is that small, a sufficient current can be caused to flow even with the drain voltage on the order of 1.5V.
However, if the pseudo state of the elongated trap space is produced, as shown in FIG. 28C, it becomes difficult to provide the channel current of the memory cell. That is, if the pseudo state equivalent to the state of the voltage Vg of 4V of the word line and the control gate is created, only small channel current flows for the drain voltage of 1.5V, while no current flows for Vg 3V.
Thus, it may be seen that the memory cell current depends appreciably on the length of the trap space and is susceptible strongly to process variations.
Referring to FIG. 29, the operation of erasing the memory cell as stated in the Publication (1) (Erase operation) is explained. The erasure operation exploits the hot hole injection phenomenon of erasing the memory cell and may be achieved by recombining the electrons trapped in the electron trap area with holes.
If, when the electrons trapped in the first node (Node1) are to be recombined, a high voltage of, for example, VBN=7.0V, is applied to the terminal of the bit diffusion region (BL1), hot holes are generated at a junction between the N-type diffusion region 202 and the P-type silicon substrate 201 due to the band-to-band tunneling phenomenon. These holes (positive holes) are attracted by the potential of the word line 206 and injected into the ONO film 204.
The holes are diffused towards the second node (Node2) as opposing the potential of the N-type diffusion region 202 of the BLI terminal. However, only a fraction of the holes are attracted by the potential of the word line 206 so as to be injected into the ONO film 204.
Moreover, if the trap space is too long, the generated holes are diffused and spread through the silicon substrate 201, so that the phenomenon of recombination is less susceptible to be produced.
The problems of the conventional semiconductor memory device, described in the above Publication (1), may be summarized as follows:
During read, the memory cell current depends on the trap space length, which is susceptible to process variations, so that no stable characteristics may be achieved.
The erasure characteristics depend on the trap space length such that the erasure characteristics are unstable.
There lacks up to now a technique of providing and realizing the trap space length which is less susceptible to process variations.
Accordingly, it is an object of the present invention to provide a semiconductor memory device in which channel current variations ascribable to e.g. size variations due to process variations may be reduced to assure a stable circuit operation.
It is another object of the present invention to provide a method for manufacturing and a method for controlling the semiconductor memory device.
The above and other objects are attained by a semiconductor memory device in accordance with one aspect of the present invention which includes a first diffusion region provided in a substrate surface, a first insulating film provided in a first area on the substrate neighboring to the first diffusion region, a first gate electrode formed on and laying the first insulating film, a second insulating film provided in a second area on the substrate neighboring to the first area, and a second gate electrode formed on and overlaying the second insulating film, constitute a unit cell. A second diffusion region is provided in a third area in the substrate surface located in an extension of the second electrode. In the unit cell, the first gate electrode intersects the second gate electrode via an insulating film. The unit cell stores one bit.
A two-bit cell transistor in accordance with another aspect of the present invention comprises unit cells arranged symmetrically to each other and includes first and second diffusion regions, provided in separation from each other in a substrate surface, first and second insulating films provided in first and second areas on the substrate neighboring to the first and second diffusion regions, respectively, first and second gate electrodes, provided on the first and second insulating films, a third insulating film provided in a third area on the substrate neighboring to the first and second areas, a third gate electrode provided on the third insulating film and a fourth insulating film provided on the third gate electrode, with the first and second diffusion regions, first and second insulating films, first and second gate electrodes, third insulating film, third gate electrode and the fourth insulating film constituting a cell for storage of the two-bit information therein. The first and second gate electrodes are connected common on the fourth insulating film to make up a word line electrode. The third gate electrode constitutes a control gate electrode extending in a direction perpendicular to the word line. A third diffusion area is provided in a fourth area in the substrate surface located on an extension of the third gate electrode.
As a layout structure of the unit cell in accordance with the present invention, a buried diffusion region is provided in the substrate surface, at one or both longitudinal ends of a control gate electrode arranged on the substrate with interposition of a first insulating layer, in an area neighboring to a first diffusion region in the substrate surface, and a first gate electrode is provided in an area between the control gate and the first diffusion region with interposition of a second insulating film including a charge trapping film. The first gate electrode is connected to a word line electrode arranged at right angles to the control gate electrode. The first diffusion region, the first gate, the control gate and the buried diffusion region form a unit cell.
As a layout structure of the unit cell, in accordance with the present invention, there are provided first and second diffusion regions arranged as two rows in a substrate surface in separation from each other, a control gate electrode arranged in an area on the substrate between the first and second layers, forming the rows, with interposition of a first insulating film, and a buried diffusion region in an area in the substrate surface at one or both longitudinal ends of the control gate electrode. There are also provided first and second gate electrodes provided in a first area between the first diffusion region and the control gate and in a second area between the second diffusion region and the control gate, respectively, with interposition of second and third insulating films, each including a charge trapping film, respectively. The first and second gate electrodes are connected to a word line electrode arranged at right angles to the control gate electrode. The first diffusion region, first gate, control gate and the buried diffusion region form a first unit cell, while the second diffusion region, second gate, control gate and the buried diffusion region form a second unit cell.
A semiconductor memory device in accordance with another aspect of the present invention comprises a plurality of rows of diffusion regions extending in a memory cell area in a substrate surface parallel to one another along one direction in separation from one another, with the plural rows of diffusion regions being connected to associated bit lines, a buried diffusion region extending in the substrate surface in a direction perpendicular to the one direction at a location spaced apart from both longitudinal ends of the plural rows of diffusion regions, a plurality of word line electrodes arranged on the substrate with interposition of a first insulating film including a charge trapping film, with the word line electrodes extending parallel to one another in a direction perpendicular to the one direction, and a plurality of control gate electrodes arranged on the substrate in adjacency to an associated one of the diffusion regions, with interposition of an insulating film, for extending along the one direction, with the control gate electrode three-dimensionally intersecting the buried diffusion region with interposition of the second insulating film.
In a semiconductor memory device, according to one aspect of the present invention, in programming of the cell, the selected word line electrode is set to a first positive voltage, a second voltage equal to a threshold voltage (Vt) or higher by a preset voltage than the threshold voltage is applied to a control gate electrode of a selected cell, a ground potential is applied to the buried diffusion region, and a third positive voltage is applied to a bit line connecting to a diffusion region closer to a storage node as a program target in the cell, so that the buried diffusion region operates as an electron supply source to effect programming by source side injection to the storage node.
According to the present invention, in cell erasure operation, the word line electrode is set to a ground potential or a negative voltage, a fifth positive voltage is applied to a bit line connecting to the diffusion region, a sixth voltage is applied to the control gate electrode and a fourth voltage is applied to the buried diffusion region to form a hole barrier in a channel directly below the control gate electrode to effect cell erasure. The fifth positive voltage is applied to all bit lines of the memory cell area, the totality of the word line electrodes in the memory cell area are at a ground potential or at a negative voltage, and the sixth positive voltage is applied to the totality of the control gate electrodes of the memory cell area to effect collective (flash) erasure of a plurality of cells in the memory cell area.
According to the present invention, in cell read operation, a seventh positive voltage is applied to the buried diffusion region, an eighth positive voltage is applied to the control gate of a cell to be read, a ground potential is applied to a bit line connected to the diffusion region closer to the storage node to be read in the cell, and a ninth positive voltage is applied to the selected word line electrode to read the cell with the buried diffusion region as the drain side. Alternatively, a ground potential is applied to the buried diffusion region, an eighth voltage is applied to the control gate of a cell to be read, a seventh positive voltage is applied to the bit line connecting to the diffusion region closer to the storage node to be read in the cell, and a ninth positive voltage is applied to the selected word line electrode to read the cell with the buried diffusion region as the source side.
A method for manufacturing a semiconductor memory device in yet another aspect of the present invention comprises the steps of:
depositing a first insulating film and a first electrically conductive film in this order on a semiconductor substrate;
depositing a second insulating film on the first electrically conductive film;
patterning a laminated film composed of the first insulating film, first electrically conductive film and the second insulating film to form a control gate;
depositing a third insulating film on the entire surface of the substrate;
depositing a second electrically conductive film on the entire surface of the substrate and subsequently processing the second electrically conductive film in the form of a sidewall on a sidewall section of the control gate covered by the third insulating film;
performing ion injecting with the control gate and with the sidewall of the second electrically conductive film as a mask to form a diffusion region in the substrate surface by self-alignment;
forming a fourth insulating film on the entire substrate surface and subsequently exposing an upper portion of the sidewall of the second electrically conductive film by polishing or etchback; and
depositing a third electrically conductive film on the entire substrate surface and subsequently removing the third electrically conductive film and the sidewall of the second electrically conductive film to form a word line.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.